Registers - vs_4_0

This section contains reference information for the input and output registers implemented by vertex shader version 4_0.

Input Registers

Register Name Count R/W Dimension Indexable by r# Defaults Requires DCL
r# 4096(r#+x#[n]) R/W 4 No None Yes
x#[n] 4096(r#+x#[n]) R/W 4 Yes None Yes
v# 16 R 4 Yes None Yes
t# 128 R 1 No None Yes
s# 16 R 1 No None Yes
cb#[index] 15 R 4 Yes(Contents) None Yes
icb[index] 1 R 4 Yes(Contents) None Yes

 

Output Registers

Register Name Count R/W Dimension Indexable by r# Defaults Requires DCL
NULL Discard Result N/A W N/A N/A N/A No
o# Output Register 16 W N/A N/A 4 Yes

 

Shader Model 4