Bagikan melalui

Coreinfo v3.6

  • Artikel

Oleh Mark Russinovich

Diterbitkan: 29 September 2022

DownloadUnduh Coreinfo(531 KB)

Pendahuluan

Coreinfo adalah utilitas baris perintah yang menunjukkan pemetaan antara prosesor logis dan prosesor fisik, node NUMA, dan soket tempat mereka berada, serta cache yang ditetapkan untuk setiap prosesor logis. Ini menggunakan fungsi GetLogicalProcessorInformation Windows' untuk mendapatkan informasi ini dan mencetaknya ke layar, mewakili pemetaan ke prosesor logis dengan tanda bintang misalnya '*'. Coreinfo berguna untuk mendapatkan wawasan tentang topologi prosesor dan cache sistem Anda.

Penginstalan

Ekstrak arsip ke direktori lalu jalankan Coreinfo dengan mengetik dari direktori Coreinfo tersebut di konsol pada versi Windows 32 bit atau Coreinfo64 untuk versi 64 bit.

Menggunakan CoreInfo

Untuk setiap sumber daya, ini menunjukkan peta prosesor yang terlihat OS yang sesuai dengan sumber daya yang ditentukan, dengan '*' mewakili prosesor yang berlaku. Misalnya, pada sistem 4-core, garis dalam output cache dengan peta dibagikan oleh inti 3 dan 4.

Penggunaan: coreinfo [-c][-f][-g][-l][-n][-s][-m][-v]

Parameter Deskripsi
-C Buang informasi pada inti.
-F Mencadangkan informasi fitur inti.
-G Buang informasi pada grup.
-L Buang informasi pada cache.
-n Buang informasi pada simpul NUMA.
-S Buang informasi pada soket.
-M Mencadangkan biaya akses NUMA.
-v Buang hanya fitur terkait virtualisasi termasuk dukungan untuk terjemahan alamat tingkat kedua.
(memerlukan hak administratif pada sistem Intel).

Semua opsi kecuali -v dipilih secara default.

Output Coreinfo:

Coreinfo v3.03 - Dump information on system CPU and memory topology
Copyright (C) 2008-2011 Mark Russinovich
Sysinternals - www.sysinternals.com

Intel(R) Xeon(R) CPU           W3520  @ 2.67GHz
Intel64 Family 6 Model 26 Stepping 5, GenuineIntel
EM64T           *       Supports 64-bit mode
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
HYPERVISOR      *       Hypervisor is present
HTT             *       Supports hyper-threading

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
EIST            *       Supports Enhanced Intel Speedstep

NX              *       Supports no-execute page protection
PAGE1GB         -       Supports 1GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4-MB pages
PSE36           *       Supports > 32-bit address 4-MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode

FPU             *       Implements i387 FP instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             -       Supports AES extensions
AVX             -       Supports AVX instruction extensions
FMA             -       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTTR            *       Supports Mmeory Type Range Registers
XSAVE           -       Supports XSAVE/XRSTOR instructions
OSXSAVE         -       Supports XSETBV/XGETBV instructions

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
DCA             -       Supports prefetch from memory-mapped device
F16C            -       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         -       Supports MONITOR and MWAIT instructions
MOVBE           -       Supports MOVBE instruction
PCLULDQ         -       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
SEP             *       Supports fast system call instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
xTPR            *       Supports disabling task priority messages

ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             *       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

Logical to Physical Processor Map:
*---  Physical Processor 0
-*--  Physical Processor 1
--*-  Physical Processor 2
---*  Physical Processor 3

Logical Processor to Socket Map:
****  Socket 0

Logical Processor to NUMA Node Map:
****  NUMA Node 0

Logical Processor to Cache Map:
*---  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
*---  Instruction Cache   0, Level 1,   32 KB, Assoc   4, LineSize  64
*---  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
-*--  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
-*--  Instruction Cache   1, Level 1,   32 KB, Assoc   4, LineSize  64
-*--  Unified Cache       1, Level 2,  256 KB, Assoc   8, LineSize  64
--*-  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
--*-  Instruction Cache   2, Level 1,   32 KB, Assoc   4, LineSize  64
--*-  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
---*  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
---*  Instruction Cache   3, Level 1,   32 KB, Assoc   4, LineSize  64
---*  Unified Cache       3, Level 2,  256 KB, Assoc   8, LineSize  64
****  Unified Cache       4, Level 3,    8 MB, Assoc  16, LineSize  64

Logical Processor to Group Map:
****  Group 0

DownloadUnduh Coreinfo(531 KB)