3DNow! Instruction Formats

Microsoft Specific

The format of 3DNow! instruction encodings is based on the conventional x86 modR/M instruction format and is similar to the format used by MMX instructions. The assembly language syntax used for the 3DNow! instructions is as follows:

3DNow! Mnemonic   mmreg1, mmreg2/mem64

The destination and source1 operand (mmreg1) must be an MMX register (MM0–MM7). The source2 operand (mmreg2/mem64) can be either an MMX register or a 64-bit memory value.

The encoding uses the opcode prefix 0Fh followed by a second opcode byte of 0Fh. To differentiate the various 3DNow! instructions, a third instruction suffix byte is used. This suffix byte occupies the same position at the end of a 3DNow! instruction as would an imm8 byte. The opcode format is as follows:

0Fh 0Fh modR/M [sib] [displacement] 3DNow!_suffix

The specific operands (mmreg1 and mmreg2/mem64) determine the values used in modR/M [sib] [displacement] and follow conventional x86 encodings. The 3DNow! suffix is determined by the actual 3DNow! instruction.

As an example, the 3DNow! PFMUL instruction can produce the following opcodes, depending on its use:



0F 0F CA B4

PFMUL    mm1, mm2

0F 0F 0B B4

PFMUL    mm1, [ebx]

0F 0F 4B 0A B4

PFMUL    mm1, [ebx+10]

26 0F 0F 0B B4

PFMUL    mm1, es:[ebx]

0F 0F 4C 83 0A B4

PFMUL    mm1, [ebx+eax*4+10]

The encoding of the two performance enhancement instructions (FEMMS and PREFETCH) uses a single opcode prefix 0Fh.

See Also


AMD 3DNow! Technology Overview and Intrinsics