Store Operations (Integer SSE2 Intrinsics)
The following store operation intrinsics and their respective instructions are functional on Intel processors supporting Streaming SIMD Extensions 2 (SSE2) instructions.
For an explanation of the syntax used in code samples in this topic, see Floating-Point Intrinsics Using Streaming SIMD Extensions.
SSE2 intrinsics use the __m128, __m128i, and __m128d data types, which are not supported on Itanium Processor Family (IPF) processors. Any SSE2 intrinsics that use the __m64 data type are not supported on x64 processors.
The emmintrin.h header file contains the declarations for the SSE2 instructions intrinsics.
void _mm_store_si128 (__m128i *p, __m128i a);
Stores 128-bit value. Address p must be 16-byte aligned.
*p := a
For more information, see _mm_store_si128.
void _mm_storeu_si128 (__m128i *p, __m128i a);
Stores 128-bit value. Address p does not need to be 16-byte aligned.
*p := a
For more information, see _mm_storeu_si128.
void _mm_maskmoveu_si128(__m128i d, __m128i n, char *p);
Conditionally store byte elements of d to address p. The high bit of each byte in the selector n determines whether the corresponding byte in d will be stored. Address p does not need to be 16-byte aligned.
if (n0) p := d0 if (n1) p := d1 ... if (n15) p := d15
For more information, see _mm_maskmoveu_si128.
void _mm_storel_epi64(__m128i *p, __m128i a);
Stores the lower 64 bits of the value pointed to by p.