Store Operations (SSE)

Microsoft Specific

The operation intrinsics listed in the following table are followed by a description of each intrinsic.

SSE intrinsics use the __m128, __m128i, and __m128d data types, which are not supported on Itanium Processor Family (IPF) processors. Any SSE intrinsics that use the __m64 data type are not supported on x64 processors.

The header file xmmintrin.h contains the declarations for the SSE intrinsics.

Memory and Initialization Store Operations

Intrinsic name


Corresponding instruction


Stores the low value


_mm_store1_ps, _mm_store_ps1

Stores the low value across all four words

MOVSS + Shuffling


Stores four values, address aligned



Stores four values, address unaligned



Stores four values, in reverse order

MOVAPS + Shuffling


Sets the low word, and passes in three high values


For an explanation of the syntax used in code samples in this topic, see Floating-Point Intrinsics Using Streaming SIMD Extensions.

See Also


Integer Intrinsics Using Streaming SIMD Extensions