NVRAM Hardware

The NVRAM must be able to hold two DWORD data types with data from the OS plus boot count information. The reliability framework component in the Microsoft® Server Appliance Kit does not read or write to any additional NVRAM blocks available in the hardware.

Microsoft recommends that the NVRAM provide memory-mapped registers to communicate with the driver. If it does not provide memory-mapped registers, replace references to reading and setting registers with reading and writing to I/O ports.

The NVRAM uses programmed I/O to transfer persistent state data between the OS and the hardware through the NVRAM driver.

Microsoft strongly recommends that the NVRAM hardware be implemented to accept an entire state update in one I/O operation. This eliminates the need for interrupt service routine (ISR) or hardware polling in the driver. The rest of this documentation assumes that the NVRAM hardware can handle reads and writes as atomic operations. If the hardware cannot receive an entire state update in one I/O operation, it may generate interrupts to signal the driver when it is ready for more data, or the driver may be required to poll the NVRAM device to see when it is ready.

Either flash Electrically Erasable Programmable Read Only Memory (EEPROM) or battery-backed complementary metal oxide semiconductor (CMOS) are recommended for the NVRAM. These memory locations must only be written at major state changes—for example, shutdown or software update—and therefore are not likely to wear out flash memory in the expected lifetime of the product.